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Stefan Westerfeld
ffmpeg
Commits
01c5f4ad
Commit
01c5f4ad
authored
May 07, 2024
by
Rémi Denis-Courmont
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riscv: add Zvbb vector bit manipulation extension
parent
11f68931
Changes
8
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8 changed files
with
12 additions
and
1 deletion
+12
-1
Makefile
Makefile
+1
-1
configure
configure
+3
-0
APIchanges
doc/APIchanges
+3
-0
arch.mak
ffbuild/arch.mak
+1
-0
cpu.c
libavutil/cpu.c
+1
-0
cpu.h
libavutil/cpu.h
+1
-0
cpu.c
libavutil/tests/cpu.c
+1
-0
checkasm.c
tests/checkasm/checkasm.c
+1
-0
No files found.
Makefile
View file @
01c5f4ad
...
...
@@ -101,7 +101,7 @@ SUBDIR_VARS := CLEANFILES FFLIBS HOSTPROGS TESTPROGS TOOLS \
ARMV5TE-OBJS ARMV6-OBJS ARMV8-OBJS VFP-OBJS NEON-OBJS
\
ALTIVEC-OBJS VSX-OBJS MMX-OBJS X86ASM-OBJS
\
MIPSFPU-OBJS MIPSDSPR2-OBJS MIPSDSP-OBJS MSA-OBJS
\
MMI-OBJS LSX-OBJS LASX-OBJS RV-OBJS RVV-OBJS
\
MMI-OBJS LSX-OBJS LASX-OBJS RV-OBJS RVV-OBJS
RVVB-OBJS
\
OBJS SLIBOBJS SHLIBOBJS STLIBOBJS HOSTOBJS TESTOBJS
define
RESET
...
...
configure
View file @
01c5f4ad
...
...
@@ -2222,6 +2222,7 @@ ARCH_EXT_LIST_PPC="
ARCH_EXT_LIST_RISCV
=
"
rv
rvv
rv_zvbb
"
ARCH_EXT_LIST_X86
=
"
...
...
@@ -2760,6 +2761,7 @@ power8_deps="vsx"
rv_deps
=
"riscv"
rvv_deps
=
"rv"
rv_zvbb_deps
=
"rvv"
loongson2_deps
=
"mips"
loongson3_deps
=
"mips"
...
...
@@ -6384,6 +6386,7 @@ elif enabled riscv; then
enabled rv
&&
check_inline_asm rv
'".option arch, +zbb\nrev8 t0, t1"'
enabled rvv
&&
check_inline_asm rvv
'".option arch, +v\nvsetivli zero, 0, e8, m1, ta, ma"'
enabled rv_zvbb
&&
check_inline_asm rv_zvbb
'".option arch, +zvbb\nvclz.v v0, v8"'
elif
enabled x86
;
then
...
...
doc/APIchanges
View file @
01c5f4ad
...
...
@@ -2,6 +2,9 @@ The last version increases of all libraries were on 2024-03-07
API changes, most recent first:
2024-05-10 - xxxxxxxxx - lavu 59.18.100 - cpu.h
Add AV_CPU_FLAG_RV_ZVBB.
2024-05-04 - xxxxxxxxxx - lavu 59.17.100 - opt.h
Add AV_OPT_TYPE_UINT and av_opt_eval_uint().
...
...
ffbuild/arch.mak
View file @
01c5f4ad
...
...
@@ -17,6 +17,7 @@ OBJS-$(HAVE_VSX) += $(VSX-OBJS) $(VSX-OBJS-yes)
OBJS-$(HAVE_RV) += $(RV-OBJS) $(RV-OBJS-yes)
OBJS-$(HAVE_RVV) += $(RVV-OBJS) $(RVV-OBJS-yes)
OBJS-$(HAVE_RV_ZVBB) += $(RVVB-OBJS) $(RVVB-OBJS-yes)
OBJS-$(HAVE_MMX) += $(MMX-OBJS) $(MMX-OBJS-yes)
OBJS-$(HAVE_X86ASM) += $(X86ASM-OBJS) $(X86ASM-OBJS-yes)
libavutil/cpu.c
View file @
01c5f4ad
...
...
@@ -192,6 +192,7 @@ int av_parse_cpu_caps(unsigned *flags, const char *s)
{
"zve64d"
,
NULL
,
0
,
AV_OPT_TYPE_CONST
,
{
.
i64
=
AV_CPU_FLAG_RVV_F64
},
.
unit
=
"flags"
},
{
"zba"
,
NULL
,
0
,
AV_OPT_TYPE_CONST
,
{
.
i64
=
AV_CPU_FLAG_RVB_ADDR
},
.
unit
=
"flags"
},
{
"zbb"
,
NULL
,
0
,
AV_OPT_TYPE_CONST
,
{
.
i64
=
AV_CPU_FLAG_RVB_BASIC
},
.
unit
=
"flags"
},
{
"zvbb"
,
NULL
,
0
,
AV_OPT_TYPE_CONST
,
{
.
i64
=
AV_CPU_FLAG_RV_ZVBB
},
.
unit
=
"flags"
},
#endif
{
NULL
},
};
...
...
libavutil/cpu.h
View file @
01c5f4ad
...
...
@@ -90,6 +90,7 @@
#define AV_CPU_FLAG_RVV_F64 (1 << 6) ///< Vectors of double's
#define AV_CPU_FLAG_RVB_BASIC (1 << 7) ///< Basic bit-manipulations
#define AV_CPU_FLAG_RVB_ADDR (1 << 8) ///< Address bit-manipulations
#define AV_CPU_FLAG_RV_ZVBB (1 << 9) ///< Vector basic bit-manipulations
/**
* Return the flags which specify extensions supported by the CPU.
...
...
libavutil/tests/cpu.c
View file @
01c5f4ad
...
...
@@ -94,6 +94,7 @@ static const struct {
{
AV_CPU_FLAG_RVV_F32
,
"zve32f"
},
{
AV_CPU_FLAG_RVV_I64
,
"zve64x"
},
{
AV_CPU_FLAG_RVV_F64
,
"zve64d"
},
{
AV_CPU_FLAG_RV_ZVBB
,
"zvbb"
},
#endif
{
0
}
};
...
...
tests/checkasm/checkasm.c
View file @
01c5f4ad
...
...
@@ -285,6 +285,7 @@ static const struct {
{
"RVVf32"
,
"rvv_f32"
,
AV_CPU_FLAG_RVV_F32
},
{
"RVVi64"
,
"rvv_i64"
,
AV_CPU_FLAG_RVV_I64
},
{
"RVVf64"
,
"rvv_f64"
,
AV_CPU_FLAG_RVV_F64
},
{
"RV_Zvbb"
,
"rv_zvbb"
,
AV_CPU_FLAG_RV_ZVBB
},
#elif ARCH_MIPS
{
"MMI"
,
"mmi"
,
AV_CPU_FLAG_MMI
},
{
"MSA"
,
"msa"
,
AV_CPU_FLAG_MSA
},
...
...
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