- 08 Nov, 2023 5 commits
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James Almer authored
Mapping to ITU-R BS.2051-3 "Sound System G" and ITU-R BS.1196-8 "Channel Configuration 20". Signed-off-by: James Almer <jamrial@gmail.com>
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James Almer authored
Mapping to ITU-R BS.2051-3 "Sound System F" and ITU-R BS.1196-8 "Channel Configuration 15". Signed-off-by: James Almer <jamrial@gmail.com>
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Henrik Gramner authored
When operating on large blocks of data it's common to repeatedly use an instruction on multiple registers. Using the REPX macro makes it easy to quickly write dense code to achieve this without having to explicitly duplicate the same instruction over and over. For example, REPX {paddw x, m4}, m0, m1, m2, m3 REPX {mova [r0+16*x], m5}, 0, 1, 2, 3 will expand to paddw m0, m4 paddw m1, m4 paddw m2, m4 paddw m3, m4 mova [r0+16*0], m5 mova [r0+16*1], m5 mova [r0+16*2], m5 mova [r0+16*3], m5 Commit taken from x264: https://code.videolan.org/videolan/x264/-/commit/6d10612ab0007f8f60dd2399182efd696da3ffe4Signed-off-by: Frank Plowman <post@frankplowman.com> Signed-off-by: Anton Khirnov <anton@khirnov.net>
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Zhao Zhili authored
Signed-off-by: Zhao Zhili <zhilizhao@tencent.com>
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Peter Ross authored
Partially fixes ticket #798 Reviewed-by: James Almer <jamrial@gmail.com> Reviewed-by: Michael Niedermayer <michael@niedermayer.cc> Reviewed-by: Paul B Mahol <onemda@gmail.com> Signed-off-by: Peter Ross <pross@xvid.org>
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- 07 Nov, 2023 1 commit
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Zhao Zhili authored
Signed-off-by: Zhao Zhili <zhilizhao@tencent.com>
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- 06 Nov, 2023 3 commits
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Rémi Denis-Courmont authored
This uses a more traditional approach allowing up processing of up to period minus two elements per iteration. This also allows the algorithm to work for all and any vector length. As the T-Head C908 device under test can load 16 elements loop, there is unsurprisingly a little performance drop when the period is minimal and the parallelism is capped at 13 elements: Before: postfilter_15_c: 21222.2 postfilter_15_rvv_f32: 22007.7 postfilter_512_c: 20189.7 postfilter_512_rvv_f32: 22004.2 postfilter_1022_c: 20189.7 postfilter_1022_rvv_f32: 22004.2 After: postfilter_15_c: 20189.5 postfilter_15_rvv_f32: 7057.2 postfilter_512_c: 20189.5 postfilter_512_rvv_f32: 5667.2 postfilter_1022_c: 20192.7 postfilter_1022_rvv_f32: 5667.2
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Rémi Denis-Courmont authored
As in the aligned case, we can use VLSE64.V, though the way of doing so gets more convoluted, so the performance gains are more modest: get_pixels_unaligned_c: 126.7 get_pixels_unaligned_rvv_i32: 145.5 (before) get_pixels_unaligned_rvv_i64: 62.2 (after) For the reference, those are the aligned benchmarks (unchanged) on the same T-Head C908 hardware: get_pixels_c: 126.7 get_pixels_rvi: 85.7 get_pixels_rvv_i64: 33.2
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Rémi Denis-Courmont authored
hf_g_filt_c: 1552.5 hf_g_filt_rvv_f32: 679.5
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- 05 Nov, 2023 5 commits
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Paul B Mahol authored
Makes better results in final output if multiple filters are cascaded at once.
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Paul B Mahol authored
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Anton Khirnov authored
Explicitly state what the implications of this are.
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Anton Khirnov authored
Partially fixes #10617
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Rob Hall authored
Without this flag, timestamps were embedded into the final binary if CUDA was enabled. Signed-off-by: Rob Hall <robxnanocode@outlook.com> Signed-off-by: Anton Khirnov <anton@khirnov.net>
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- 04 Nov, 2023 18 commits
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Paul B Mahol authored
More user-friendly and self-explanatory what certain mode does.
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Paul B Mahol authored
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Andreas Rheinhardt authored
Fixes: VUI extension leak Fixes: 63004/clusterfuzz-testcase-minimized-ffmpeg_BSF_VVC_METADATA_fuzzer-4928832253329408 Found-by: continuous fuzzing process https://github.com/google/oss-fuzz/tree/master/projects/ffmpegSigned-off-by: Andreas Rheinhardt <andreas.rheinhardt@outlook.com>
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Andreas Rheinhardt authored
Signed-off-by: Andreas Rheinhardt <andreas.rheinhardt@outlook.com>
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Andreas Rheinhardt authored
Redundant since ea043cc5 (which made 16x16 no longer use MMX). Signed-off-by: Andreas Rheinhardt <andreas.rheinhardt@outlook.com>
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Andreas Rheinhardt authored
Unnecessary now that the pixelutils API abides by the ABI. Signed-off-by: Andreas Rheinhardt <andreas.rheinhardt@outlook.com>
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Andreas Rheinhardt authored
We currently mostly do not empty the MMX state in our MMX DSP functions; instead we only do so before code that might be using x87 code. This is a violation of the System V i386 ABI (and maybe of other ABIs, too): "The CPU shall be in x87 mode upon entry to a function. Therefore, every function that uses the MMX registers is required to issue an emms or femms instruction after using MMX registers, before returning or calling another function." (See 2.2.1 in [1]) This patch does not intend to change all these functions to abide by the ABI; it only does so for ff_pixelutils_sad_8x8_mmxext, as this function can by called by external users, because it is exported via the pixelutils API. Without this, the following fragment will assert (on x86/x64): uint8_t src1[8 * 8], src2[8 * 8]; av_pixelutils_sad_fn fn = av_pixelutils_get_sad_fn(3, 3, 0, NULL); fn(src1, 8, src2, 8); av_assert0_fpu(); [1]: https://raw.githubusercontent.com/wiki/hjl-tools/x86-psABI/intel386-psABI-1.1.pdfSigned-off-by: Andreas Rheinhardt <andreas.rheinhardt@outlook.com>
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Andreas Rheinhardt authored
Signed-off-by: Andreas Rheinhardt <andreas.rheinhardt@outlook.com>
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Andreas Rheinhardt authored
Signed-off-by: Andreas Rheinhardt <andreas.rheinhardt@outlook.com>
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Andreas Rheinhardt authored
Signed-off-by: Andreas Rheinhardt <andreas.rheinhardt@outlook.com>
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Andreas Rheinhardt authored
Signed-off-by: Andreas Rheinhardt <andreas.rheinhardt@outlook.com>
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Andreas Rheinhardt authored
Signed-off-by: Andreas Rheinhardt <andreas.rheinhardt@outlook.com>
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Andreas Rheinhardt authored
Signed-off-by: Andreas Rheinhardt <andreas.rheinhardt@outlook.com>
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Andreas Rheinhardt authored
Signed-off-by: Andreas Rheinhardt <andreas.rheinhardt@outlook.com>
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Andreas Rheinhardt authored
Also avoid using the avfilter-prefix for static objects. Signed-off-by: Andreas Rheinhardt <andreas.rheinhardt@outlook.com>
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Andreas Rheinhardt authored
Signed-off-by: Andreas Rheinhardt <andreas.rheinhardt@outlook.com>
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Andreas Rheinhardt authored
Signed-off-by: Andreas Rheinhardt <andreas.rheinhardt@outlook.com>
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Andreas Rheinhardt authored
swb_offset_960_48 and swb_offset_960_32 coincide. Signed-off-by: Andreas Rheinhardt <andreas.rheinhardt@outlook.com>
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- 03 Nov, 2023 6 commits
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Michael Niedermayer authored
Fixes: Timeout Fixes: 63661/clusterfuzz-testcase-minimized-ffmpeg_dem_LAF_fuzzer-6615365234589696 Found-by: continuous fuzzing process https://github.com/google/oss-fuzz/tree/master/projects/ffmpegReviewed-by: Sean McGovern <gseanmcg@gmail.com> Signed-off-by: Michael Niedermayer <michael@niedermayer.cc>
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Michael Niedermayer authored
Fixes: out of array write Fixes: 63520/clusterfuzz-testcase-minimized-ffmpeg_AV_CODEC_ID_FLIC_fuzzer-4876198087622656 Regression since: c7f8d42c (was not posted to ffmpeg-devel) Found-by: continuous fuzzing process https://github.com/google/oss-fuzz/tree/master/projects/ffmpegReviewed-by: Sean McGovern <gseanmcg@gmail.com> Signed-off-by: Michael Niedermayer <michael@niedermayer.cc>
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Michael Niedermayer authored
Reviewed-by: Sean McGovern <gseanmcg@gmail.com> Reviewed-by: Nicolas George <george@nsup.org> Signed-off-by: Michael Niedermayer <michael@niedermayer.cc>
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Michael Niedermayer authored
Reviewed-by: Sean McGovern <gseanmcg@gmail.com> Reviewed-by: Nicolas George <george@nsup.org> Signed-off-by: Michael Niedermayer <michael@niedermayer.cc>
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Andreas Rheinhardt authored
Addresses the issue reported in ticket #4609. Signed-off-by: Andreas Rheinhardt <andreas.rheinhardt@outlook.com>
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Zhao Zhili authored
Signed-off-by: Zhao Zhili <zhilizhao@tencent.com>
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- 02 Nov, 2023 2 commits
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Reimar Döffinger authored
This is cleaner, but it is also a workaround for when the header exists, but cannot be compiled. This will happen when the compiler has no inline asm support. Possibly the configure check should be improved as well.
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Reimar Döffinger authored
Fixes compilation with tcc, which does not have aarch64 inline asm support.
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