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uplex-varnish
varnishevent3
Commits
61cc67d4
Commit
61cc67d4
authored
Mar 02, 2011
by
Poul-Henning Kamp
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Try to handle ttl and grace next to each other.
parent
d6b33885
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cache_center.c
bin/varnishd/cache_center.c
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bin/varnishd/cache_center.c
View file @
61cc67d4
...
@@ -528,6 +528,7 @@ cnt_fetch(struct sess *sp)
...
@@ -528,6 +528,7 @@ cnt_fetch(struct sess *sp)
sp
->
wrk
->
entered
=
TIM_real
();
sp
->
wrk
->
entered
=
TIM_real
();
sp
->
wrk
->
age
=
0
;
sp
->
wrk
->
age
=
0
;
sp
->
wrk
->
exp
.
ttl
=
RFC2616_Ttl
(
sp
);
sp
->
wrk
->
exp
.
ttl
=
RFC2616_Ttl
(
sp
);
sp
->
wrk
->
exp
.
grace
=
NAN
;
/*
/*
* Initial cacheability determination per [RFC2616, 13.4]
* Initial cacheability determination per [RFC2616, 13.4]
...
@@ -552,7 +553,6 @@ cnt_fetch(struct sess *sp)
...
@@ -552,7 +553,6 @@ cnt_fetch(struct sess *sp)
sp
->
wrk
->
exp
.
ttl
=
-
1
.;
sp
->
wrk
->
exp
.
ttl
=
-
1
.;
sp
->
wrk
->
do_esi
=
0
;
sp
->
wrk
->
do_esi
=
0
;
sp
->
wrk
->
exp
.
grace
=
NAN
;
sp
->
wrk
->
body_status
=
RFC2616_Body
(
sp
);
sp
->
wrk
->
body_status
=
RFC2616_Body
(
sp
);
...
...
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