• Rémi Denis-Courmont's avatar
    lavu/cpu: CPU flags for the RISC-V Vector extension · 0c0a3deb
    Rémi Denis-Courmont authored
    RVV defines a total of 12 different extensions, including:
    
    - 5 different instruction subsets:
      - Zve32x: 8-, 16- and 32-bit integers,
      - Zve32f: Zve32x plus single precision floats,
      - Zve64x: Zve32x plus 64-bit integers,
      - Zve64f: Zve32f plus Zve64x,
      - Zve64d: Zve64f plus double precision floats.
    
    - 6 different vector lengths:
      - Zvl32b (embedded only),
      - Zvl64b (embedded only),
      - Zvl128b,
      - Zvl256b,
      - Zvl512b,
      - Zvl1024b,
    
    - and the V extension proper: equivalent to Zve64f and Zvl128b.
    
    In total, there are 6 different possible sets of supported instructions
    (including the empty set), but for convenience we allocate one bit for
    each type sets: up-to-32-bit ints (RVV_I32), floats (RVV_F32),
    64-bit ints (RVV_I64) and doubles (RVV_F64).
    
    Whence the vector size is needed, it can be retrieved by reading the
    unprivileged read-only vlenb CSR. This should probably be a separate
    helper macro if needed at a later point.
    0c0a3deb
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