Retune SHA2 code for improved performance on CPUs with more ILP and
a preference for memory load instructions over large code footprints
with embedded immediate variables.

On amd64 CPUs from 2007-2008 there is not a significant change, but
amd64 CPUs from 2009-2010 get roughly 10% more throughput with this
code; amd64 CPUs from 2011-2012 get roughly 15% more throughput; and
AMD64 CPUs from 2013-2015 get 20-25% more throughput.  The Raspberry
Pi 2 increases its throughput by 6-8%.

Sponsored by:   Tarsnap Backup Inc.

The generated code needs a larger stack when optimizations are
disabled, i.e. with --enable-debugging-symbols.

(One of the thing you'd think ISO-C had solved long time ago...)

put a pid-file in the workdir.

Improve the collision error message for -P by including the other pid.

Because of Transient storage being a special-case stevedore, the
STV_Foreach logic would only work after the child's startup once
all storage backends are defined. So during the setup, collisions
would only be detected for the Transient storage.

The underlying STV__iter function is now pretty much like a plain
VTAILQ_FOREACH loop with an additional CHECK_OBJ_ORNULL step on all
iterations.

As a result, the transient storage is appended to the list at the
end of the manager's setup and is now reported last in the CLI's
storage.list command.

Error messages related to the -s option are slightly more helpful.

Fixes #2321

Inspired by:

https://git.alpinelinux.org/cgit/aports/plain/main/varnish/musl-mode_t.patch?h=3.5-stable

From upstream:

Avoid left shift of a negative value in flush rank calculation.
The C standard permits an undefined result for a left shift of a
negative value.

more characters are necessary.

Use fprintf(stderr,...) for progress messages.
I doubt we need a VUT_Msg() for that, given that only one use was
from outside vut.c, and that is probably an API mistake.